As scaling down of the feature size of MOSFETs continuously, the proportion of parasitic resistance in the total resistance of the device is growing, which seriously restricts the enhancement of properties of small size devices. The existing structure/method to reduce parasitic resistance comprises forming raised source/drain, forming a metal silicide in/on the source/drain region, increasing contact area, and so on.
However, no matter which structure/method is used, there is still a large distance between the contact area (or the contact hole, CA) and the gate spacer, and the distance the carriers of electrons/holes span from the source region to the drain region through the channel region is still large. Thus, parasitic resistance still cannot be effectively reduced and the enhancement of the device performance is limited.